HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 916

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.11 Receive Data Frame Pending Registers 1 and 0 (CANRXPR1, CANRXPR0)
The CANRXPR are two 16-bit read/conditionally-write registers that contain the receive Data
Frame pending flags associated with the configured Receive Mailboxes. When a CAN Data Frame
is successfully stored in a receive Mailbox, the corresponding bit is set in CANRXPR. The bit
may be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect.
However, the bit may only be set if the Mailbox is configured by its MBC (Mailbox
Configuration) to receive Data Frame. When a CANRXPR bit is set, it also set IRR1 (Data Frame
Received Interrupt Flag) if its CANMBIMR (Mailbox Interrupt Mask Register) is not set, and the
interrupt signal is generated if IMR1 is not set. Please note that those bits are only set by receiving
Data Frame and not by receiving Remote Frame.
• CANRXPR1
Initial value:
Note: * Only a write of 1 is allowed to clear the bit.
• CANRXPR0
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 832 of 1330
REJ09B0554-0200
15 to 0
Bit
R/W:
R/W:
Bit:
Bit:
RXPR1
RXPR1[15:0]
RXPR0
R/W*
R/W*
_15
_15
15
15
0
0
Bit Name
RXPR1
RXPR0
R/W*
R/W*
_14
_14
14
14
0
0
RXPR1
RXPR0
R/W*
R/W*
_13
_13
13
13
0
0
RXPR1
RXPR0
R/W*
R/W*
All 0
_12
_12
12
Initial Value
12
0
0
RXPR1
RXPR0
R/W*
R/W*
_11
_11
11
11
0
0
RXPR1
RXPR0
R/W*
R/W*
_10
_10
10
10
0
0
R/W*
RXPR1
RXPR0
R/W*
R/W*
R/W
_9
_9
9
0
9
0
RXPR1
RXPR0
R/W*
R/W*
_8
_8
8
0
8
0
Configurable receive Mailbox locations
corresponding to Mailbox position from 31 to
16 respectively.
0: Clearing condition: Write a 1 to this bit.
1: Corresponding Mailbox received a CAN
RXPR1
RXPR0
R/W*
Data Frame.
Setting condition: Completion of Data
Frame receive on corresponding Mailbox
R/W*
_7
_7
7
0
7
0
RXPR1
RXPR0
R/W*
R/W*
_6
_6
0
0
6
6
RXPR1
RXPR0
R/W*
R/W*
_5
_5
5
0
5
0
Description
RXPR1
RXPR0
R/W*
R/W*
_4
_4
4
0
4
0
RXPR1
RXPR0
R/W*
R/W*
_3
_3
3
0
3
0
RXPR1
RXPR0
R/W*
R/W*
_2
_2
2
0
2
0
RXPR1
RXPR0
R/W*
R/W*
_1
_1
1
0
1
0
RXPR1
RXPR0
R/W*
R/W*
_0
_0
0
0
0
0