HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 766

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Section 19 I
• Transmit Data Register (ICTXD) (FIFO Buffer Mode)
Initial value:
Initial value:
19.3.11 FIFO Control Register (ICFCR)
ICFCR is a register for resetting the byte count and setting the number of trigger data in transmit
and receive FIFO registers, respectively. ICFCR can always be read from and written to by the
CPU.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 682 of 1330
REJ09B0554-0200
Bit
31 to 8
ICTXD is a 16-stage FIFO register for storing the transmit data. When the data is written to the
ICTXD and the shift register is empty, the data is transferred from ICTXD to the shift register
and transmission starts.
ICTXD is write only and cannot be read from by the CPU. When the register is full with 16
bytes of data, the subsequent data cannot be written to, and the written value is ignored.
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Bit Name
31
15
31
15
2
W
W
R
R
0
0
-
-
-
-
-
-
C Bus Interface
30
14
30
14
W
W
-
-
-
-
-
R
-
R
0
0
29
13
29
13
W
W
R
R
0
0
-
-
-
-
-
-
Initial Value
All 0
28
12
28
12
W
W
R
R
0
0
-
-
-
-
-
-
27
11
27
11
W
W
R
R
0
0
-
-
-
-
-
-
R/W
R
26
10
26
10
W
W
R
R
-
-
-
-
-
0
-
0
25
25
W
W
R
R
-
-
9
-
-
-
0
9
-
0
Description
Reserved.
These bits are always read as 0. The write value
should always be 0.
24
24
W
W
R
R
8
8
0
0
-
-
-
-
-
-
RTRG3
R/W
23
23
W
W
R
7
-
0
7
0
-
-
-
RTRG2 RTRG1
R/W
22
22
W
W
-
R
6
6
0
0
-
-
-
R/W
21
21
W
W
R
5
-
0
5
0
-
-
-
RTRG0 TTRG1
R/W
20
20
W
W
R
4
4
-
0
0
-
-
-
TXD
R/W
19
19
W
W
R
3
-
0
3
0
-
-
-
TTRG0 RFRST TFRST
R/W
18
18
W
W
R
2
-
2
0
0
-
-
-
R/W
17
17
W
W
R
-
1
0
1
0
-
-
-
R/W
16
16
W
W
R
0
0
-
0
0
-
-
-

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