HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 398

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2) Wait State Control
Wait-state insertion for the SRAM interface can be controlled by WCR2. If the wait-control bits
for each area in WCR2 are not zero, a software wait is inserted in accordance with the wait-control
bits. For details, see section 10.5.6, Wait Control Register 2 (WCR2).
A specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing
shown in figure 10.10.
Rev. 2.00 Feb. 12, 2010 Page 314 of 1330
REJ09B0554-0200
Figure 10.10 SRAM Interface Wait Timing (Software Wait Only)
Note:
CKIO
A25–A0
CSn
RD/WR
RD
D31–D0
(read)
WEn
D31–D0
(write)
BS
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn
of the DMAC is cleared to 0.
T1
Tw
T2