HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 500

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.14 DMA Audio Control Register (DMAACR)
DMAACR is a 32-bit readable/writable register that specifies the DMA operating mode of the
HAC or SSI codec. DMAACR0 corresponds to HAC(0) or SSI(0) and DMAACR1 corresponds to
HAC(1) or SSI(1).
Initial value:
Initial value:
Bit
31 to 26 ⎯
25
24
23 to 19 ⎯
18
Rev. 2.00 Feb. 12, 2010 Page 416 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
Bit Name
RAM1
RAM0
RAR
31
15
0
R
0
R
-
-
30
14
0
R
0
R
-
-
29
13
0
0
R
R
-
-
Initial Value
All 0
0
0
All 0
0
28
12
0
R
0
R
-
-
27
11
0
0
R
R
-
-
26
10
R
R
-
0
-
0
R/W
R
R/W
R/W
R
R/W
RAM1
TAM1
R/W
R/W
25
0
0
9
RAM0
TAM0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Data Alignment Setting
These bits specify the data alignment method for
writing receive data to an external memory. For
details of the data alignment method for the
receive slot data and external bus, see table 11.5
(1).
00: Alignment control is not performed
01: Longword data is transferred as four byte-data
10: Longword data is transferred as two word-data
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Auto Reload Setting
Specifies the use or unuse of auto address reload
to continue a DMA transfer when the number of
bytes in the receive DMA transfer reaches the
number of transfer bytes specified by
DMAARXTCRn.
0: Address of receive DMA not auto reloaded
1: Address of receive DMA auto reloaded
R/W
R/W
24
0
0
8
23
R
R
0
0
7
-
-
22
R
R
0
0
6
-
-
21
R
R
0
0
5
-
-
20
R
R
0
4
0
-
-
19
R
R
0
0
-
3
-
R/W
R/W
RAR
TAR
18
2
0
0
RDS
R/W
TDS
R/W
17
0
0
1
RDE
TDE
R/W
R/W
16
0
0
0