HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1036

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In multiblock transfer, the transfer clock output should be temporarily halted at every block break
to select either to continue to the next block or to abort the multiblock transfer command by
issuing the CMD12 command, and the transfer clock output should be resumed. To continue to the
next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command,
the CMDOFF bit should be set to 1 to abort the command sequence on the MMCIF side.
Note: The FIFO full interrupt source must be cleared (FIFO data read) only after five or more
26.3.9
CTOCR specifies the period to generate a timeout for the command response.
The counter (CTOUTC), to which the peripheral bus does not have access, counts the transfer
clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts
counting the transfer clock from the start of command transmission. CTOUTC is cleared and stops
counting the transfer clock when command response reception has been completed, or when the
command sequence has been aborted by setting the CMDOFF bit to 1.
When the command response cannot be received, CTOUTC continues counting the transfer clock,
and enters the command timeout error state when the number of transfer clock cycles reaches the
number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in
INTSTR1 is set. As CTOUTC continues counting transfer clock, the CTERI flag setting condition
is repeatedly generated. To perform command timeout error handling, the command sequence
should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be cleared to
prevent extra-interrupt generation.
Rev. 2.00 Feb. 12, 2010 Page 952 of 1330
REJ09B0554-0200
Bit
7 to 2
transfer clock cycles have been passed since the interrupt occurred.
Command Timeout Control Register (CTOCR)
Bit
Name
—
Initial value:
Initial
Value
All 0
R/W:
Bit:
R/W
R
-
R
7
0
6
0
R
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
4
0
R
-
R
3
-
0
2
0
R
-
CTSEL1
R/W
0
1
CTSEL0
R/W
0
0