HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 893

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
5
Bit Name
MCR5
Initial Value
0
R/W
R/W
Description
Sleep Mode
Enables/disables Sleep mode transition. If this bit
is set, the Sleep Mode is enabled. The HCAN2
waits for the completion of the current bus activity
before shutting down. Until this mode is
terminated HCAN2 will ignore all CAN bus
activities. The two Error Counters (TEC and REC)
will remain the same values during Sleep mode.
Sleep mode will be exited in two ways:
•
•
When leaving this mode, the HCAN2 will
synchronize to the CAN bus (by checking for 11
recessive bits) before re-initializing. This means
that, when the second method above is used, the
HCAN2 will miss the first message to receive,
however, CAN transceivers have the same
feature, and the software needs to be designed in
this manner.
Important: This mode is same as setting the
0: HCAN2 sleep mode is released.
1: Transition to HCAN2 sleep mode is enabled.
By writing a 0 to this bit.
If MCR7 is enabled after detecting the
dominant bit on the CAN bus.
module to the Halt mode and stopping the
clock. This means that, the interrupt is
generated from IRR0 when entering the
Sleep mode. During the Sleep mode, only
the MPI block is accessible, i.e.,
CANMCR/CANGSR/CANIRR/CANIMR
are accessible. However, for example,
IRR1 cannot be cleared as it is an OR'ed
signal of CANRXPR that cannot be
cleared during the Sleep mode, therefore,
it is recommended to set the Halt mode
first and then transit to the Sleep mode
Rev. 2.00 Feb. 12, 2010 Page 809 of 1330
REJ09B0554-0200
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