HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 506

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
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10 000
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HD6417760BL200AV
Manufacturer:
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11.3.19 DMA USB R/W Size Register (DMAURWSZ)
DMAURWSZ is a 32-bit readable/writable register that specifies the transfer direction and data
size. During USB DMA transfer, the register value can be read but cannot be modified.
Initial value:
Initial value:
Bit
31 to 17 ⎯
16
15 to 13 ⎯
12 to 0
Rev. 2.00 Feb. 12, 2010 Page 422 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
Bit Name
RW
SZ12 to SZ0
31
15
0
R
0
R
-
-
30
14
0
R
0
R
-
-
29
13
0
0
R
R
-
-
Initial Value
All 0
0
All 0
All 0
SZ12
R/W
28
12
0
R
0
-
SZ11
R/W
27
11
0
0
R
-
SZ10
R/W
26
10
R
-
0
0
R/W
R
R/W
R
R/W
R/W
SZ9
25
R
0
0
9
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Direction
0: Specifies a DMA transfer from synchronous
1: Specifies a DMA transfer from the shared
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Data Size
Specifies the number of bytes to be transferred in
a USB DMA transfer. Up to 8191 bytes can be
specified. Setting these bits as H'0000 (SZ[12:0] =
H'0000) will not perform transfer, but setting the
START bit in DMAUCR to 1 sets the UTF bit in
DMABRGCR to 1.
R/W
SZ8
24
R
0
0
-
8
DRAM to the shared memory
memory to synchronous DRAM
R/W
SZ7
23
R
0
0
7
-
SZ6
R/W
22
R
0
0
6
-
R/W
SZ5
21
R
0
0
5
-
R/W
SZ4
20
R
0
4
0
-
R/W
SZ3
19
R
0
0
-
3
R/W
SZ2
18
R
2
0
0
-
R/W
SZ1
17
R
0
0
1
-
R/W
R/W
SZ0
RW
16
0
0
0

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