HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 52

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.7 Usage Notes ..................................................................................................................... 848
Section 23 Serial Protocol Interface (HSPI)..................................................... 849
23.1 Features............................................................................................................................ 849
23.2 Input/Output Pins ............................................................................................................. 850
23.3 Register Descriptions ....................................................................................................... 851
23.4 Operation ......................................................................................................................... 861
23.5 Power Saving and Clocking Strategy............................................................................... 865
Section 24 Pin Function Controller (PFC) ....................................................... 867
24.1 Features............................................................................................................................ 867
24.2 Register Descriptions ....................................................................................................... 870
Rev. 2.00 Feb. 12, 2010 Page l of lxxxii
REJ09B0554-0200
22.6.1 Test Mode Settings ............................................................................................. 840
22.6.2 HCAN2 Settings ................................................................................................. 841
22.6.3 Message Transmission Sequence........................................................................ 842
22.6.4 Message Reception Sequence ............................................................................. 845
22.6.5 Reconfiguration of Mailbox................................................................................ 846
22.6.6 Standby Mode ..................................................................................................... 848
22.7.1 Auto-Acknowledge Mode Usage Note ............................................................... 848
22.7.2 Mailbox Access during HCAN2 Sleep Mode..................................................... 848
23.3.1 Control Register (SPCR)..................................................................................... 852
23.3.2 Status Register (SPSR) ....................................................................................... 854
23.3.3 System Control Register (SPSCR)...................................................................... 857
23.3.4 Transmit Buffer Register (SPTBR)..................................................................... 859
23.3.5 Receive Buffer Register (SPRBR) ...................................................................... 860
23.4.1 Operation Overview without DMA (FIFO Mode Disabled)............................... 861
23.4.2 Operation Overview with DMA ......................................................................... 862
23.4.3 Operation with FIFO Mode Enabled .................................................................. 862
23.4.4 Timing Diagrams ................................................................................................ 863
23.4.5 HSPI Software Reset........................................................................................... 864
23.4.6 Clock Polarity and Transmit Control .................................................................. 864
23.4.7 Transmit and Receive Routines .......................................................................... 864
24.2.1 Port A Control Register (PACR) ........................................................................ 873
24.2.2 Port B Control Register (PBCR)......................................................................... 874
24.2.3 Port C Control Register (PCCR)......................................................................... 875
24.2.4 Port D Control Register (PDCR) ........................................................................ 876
24.2.5 Port E Control Register (PECR) ......................................................................... 878
24.2.6 Port F Control Register (PFCR).......................................................................... 879
24.2.7 Port G Control Register (PGCR) ........................................................................ 880
24.2.8 Port H Control Register (PHCR) ........................................................................ 881
24.2.9 Port J Control Register (PJCR) ........................................................................... 883
24.2.10 Port K Control Register (PKCR) ........................................................................ 884