HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 867

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.5
21.5.1
The USB host assumes that data will be stored sequentially, in little endian order, from low to high
addresses, regardless of the CPU endian setting. Figure 21.3 shows USB read operation.
The data in memory mentioned above and the data read by the USB host must always correspond.
When reading data from external memory, the USB host always reads data in longword units
regardless of the endian setting. The USB host assumes that read data is in the little endian order,
that is, the byte order that places the first byte in the lowest address and the last byte in the highest
address. That is, during operation of this IC, data must be stored sequentially in longword units in
little endian order from low to high addresses, regardless of whether the endian setting is little
endian or big endian.
An example of failure is shown in figure 21.4.
In this example, USB host controller does not receive #H'12, which is the expected transfer data.
The USB host controller, when writing, stores data sequentially starting with the low order bits in
memory in little endian order, so that the data is read/written correctly from both sides regardless
of the endian setting. That is, the data is always aligned in little endian format.
DATA.L
DATA.L
DATA.L
Data Storage Format for USB Host Controller
Storage Format of Transfer Data
The transfer address A is specified in the program (big endian mode).
The transfer start address A and 1-byte transfer size for USB is specified.
+3
12
Program
H'1122 3344
H'5566 7788
H'0000 0099
Memory
+2
00
MOV.B #H'12. @R0
Figure 21.4 Example of Transfer Failure
+1
00
Figure 21.3 USB Read Operation
+0
00
+11
+3
+7
11
55
00
Shared memory
LW read H'1200 0000
+10
Actually transferred data
+2
22
+6
66
00
Data expected to be transferred
+1
+5
+9
33
77
00
+0
+4
+8
44
88
99
Rev. 2.00 Feb. 12, 2010 Page 783 of 1330
LW read H'1122 3344
LW read H'5566 7788
LW read H'0000 0099
USB host
REJ09B0554-0200