HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 462

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

go to the high-impedance state. These bus control signals are negated no later than one cycle
before going to high-impedance. The bus request signal is sampled at the rising edge of the clock.
The following is the specific bus reacquiring sequence from the slave.
As soon as BREQ negation is detected at the rising edge of the clock, BACK is negated and the
bus control signal driving is started from next rising edge of the clock. Driving of the address bus
and data bus also starts at the same rising edge of the clock. The bus control signals are asserted
and the bus cycle is actually started, at the earliest, at the next rising edge of the clock where the
driving of the bus control signals was started.
In order to reacquire the bus and start execution of a refresh operation or bus access, the BREQ
signal must be negated for at least two cycles.
If a refresh request is generated when BACK has been asserted and the bus has been released, the
BACK signal is negated even while the BREQ signal is asserted to request a slave to release the
bus. When this LSI is used in master mode with slaves designed independently by the user,
consecutive bus accesses may be attempted to reduce the overhead due to arbitration. When
connecting a slave where the total duration of consecutive accesses exceeds the refresh cycle, it
should be designed so that the bus is released as soon as possible after negation of the BACK
signal is detected.
10.7
10.7.1
Auto refresh operations are not carried out when this LSI enters software standby, hardware
standby, or deep-sleep mode. If the memory system requires refresh operations, set the memory in
the self-refresh state prior to making the transition to software standby, hardware standby, or deep-
sleep mode.
10.7.2
The bus is not released when this LSI enters software standby or deep-sleep mode. In systems
performing bus arbitration, clear the bus release request enable bit (BCR1.BREQEN) to 0 for the
processor in master mode before making the transition to software standby or deep-sleep mode.
Correct operation is not guaranteed when a transition is made to software standby mode or deep-
sleep mode with BCR1.BREQEN = 1.
Rev. 2.00 Feb. 12, 2010 Page 378 of 1330
REJ09B0554-0200
Usage Notes
Refresh
Bus Arbitration