HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 61

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Figure 1.1
Figure 1.2
Figure 1.3
Section 2 Programming Model
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Section 3 Floating-Point Unit (FPU)
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Section 5 Pipelining
Figure 5.1
Figure 5.2
Figure 5.2
Figure 5.2
Figure 5.2
Figure 5.2
Figure 5.3
Figure 5.3
Figure 5.3
Figure 5.3
Section 6 Memory Management Unit (MMU)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
SH7760 Block Diagram .........................................................................................10
SH7760 Pin Arrangement (BP-256F/BP-256FV) ..................................................11
SH7760 Pin Arrangement (BP-256B/BP-256BV) .................................................12
Data Formats ..........................................................................................................39
CPU Register Configuration in Each Processing Mode .........................................42
General Registers ................................................................................................... 43
Data Formats in Memory .......................................................................................48
Processing State Transitions...................................................................................49
Format of Single-Precision Floating-Point Number...............................................51
Format of Double-Precision Floating-Point Number .............................................51
Single-Precision NaN Bit Pattern ...........................................................................54
Floating-Point Registers .........................................................................................56
Basic Pipelines .......................................................................................................88
Instruction Execution Patterns................................................................................89
Instruction Execution Patterns (cont) .....................................................................90
Instruction Execution Patterns (cont) .....................................................................91
Instruction Execution Patterns (cont) .....................................................................92
Instruction Execution Patterns (cont) .....................................................................93
Examples of Pipelined Execution...........................................................................100
Examples of Pipelined Execution (cont) ................................................................101
Examples of Pipelined Execution (cont) ................................................................102
Examples of Pipelined Execution (cont) ................................................................103
Role of the MMU ...................................................................................................115
Physical Address Space (AT = 0 in MMUCR) ......................................................116
P4 Area...................................................................................................................117
External Memory Space .........................................................................................118
Virtual Address Space (AT = 1 in MMUCR).........................................................119
UTLB Configuration ..............................................................................................128
Relationship between Page Size and Address Format............................................128
ITLB Configuration................................................................................................131
Figures
Rev. 2.00 Feb. 12, 2010 Page lix of lxxxii
REJ09B0554-0200