HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 181

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 5.2
Legend:
O: Can be executed in parallel
X: Cannot be executed in parallel
5.3
This LSI has three basic clocks: CPU clock (Ick), bus clock (Bck), and peripheral clock (Pck).
Each hardware unit operates on one of these clocks, as follows:
• CPU clock: CPU, FPU, MMU, cache
• Bus clock: External bus controller
• Peripheral clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the CPU clock unless otherwise specified.
For details on FRQCR, see section 12, Clock Pulse Generator (CPG).
Instruction execution cycles are summarized in table 5.3. Penalty cycles due to a pipeline stall are
not considered in this table.
• Issue rate: Interval between the issue of an instruction and that of the next instruction
• Latency: Interval between the issue of an instruction and the generation of its result
• Instruction execution pattern (see figure 5.2)
• Locked pipeline stage: Pipeline stage which has been locked
• Lock start: Interval between the issue of an instruction and the start of locking (see table 5.3)
• Lock cycle: Period of locking (see table 5.3)
1st
Instruction
(completion)
Execution Cycles and Pipeline Stalling
Parallel-Executability
MT
EX
BR
LS
FE
CO
MT
O
O
O
O
O
X
EX
O
O
O
O
X
X
2nd Instruction
BR
O
O
O
O
X
X
Rev. 2.00 Feb. 12, 2010 Page 97 of 1330
LS
O
O
O
O
X
X
FE
O
O
O
O
X
X
REJ09B0554-0200
CO
X
X
X
X
X
X