HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1182

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.4.5
The display resolution is set with the LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and
LDVSYNR. The LCD current-alternating period for STN or DSTN display is set by using the
LDACLNR. The initial values in these registers are set to VGA (640 × 480 dots), a typical
resolution for STN or DSTN display.
The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the
display interval of one screen (as specified by a size-related register) + retrace line interval (non-
display interval), and by the frequency of the clock used.
This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the
beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last
line of the display). This function is set up by using the LDINTR.
30.4.6
The LCD module normally requires processing of a specific sequence for cutting off of the input
power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD
power-supply control pins (VCPWC, VEPWC, and LCD_DON), are used to provide processing of
power-supply control sequences that suits the requirements of the LCD module.
Figures 30.4 to 30.7 are summary timing charts for power-supply control sequences and table 30.5
is a summary of available power-supply control sequence periods.
Rev. 2.00 Feb. 12, 2010 Page 1098 of 1330
REJ09B0554-0200
Setting the Display Resolution
Power Supply Control Sequence Processing