HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 778

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
5. Data transmission is done in units of eight bits plus one bit of ACK, i.e., in units of nine bits.
6.
7.
The timings of (1) to (6) in figure 19.9 are generated after the falling edge of the clock signal.
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REJ09B0554-0200
An interrupt by MDE (bit 3) is generated at the ninth clock before starting data transfer (in the
timing of (2) in figure 19.9). An interrupt by MDT (bit 2) is generated at the eighth clock after
1-byte data transfer (in the timing of (4) in figure 19.9). Clear MDE to 0 after setting transmit
data. An interrupt by the SDR bit (slave data reception) is generated at the eighth clock (in the
timing of (6) in figure 19.9). Clear the SDR bit to 0 after the slave device reads the receive
data. If this processing is delayed, the slave device extends the SCL period to suspend data
transmission (in the timing of (8) in figure 19.9).
To end data transfer, an interrupt by the MNR (bit 6) in the master status register is generated
at the ninth clock while the ACK signal from the slave device is 1 (NACK) (in the timing of
(5) in figure 19.9). The master device outputs a data transfer end condition when receiving the
NACK.
When the master device completes the data transmission, set FSB (bit 1) to 1 in the master
control register to output a force stop condition. When the last bit of a byte is
transmitted/received, the I
Therefore, to stop the transfer after a specified byte is transferred, the FSB bit must be set to 1
before the last byte data is transferred.
The FSB bit must be set to 1 before the last byte is transferred. In master transmit mode, after
the last byte is set, the MST (master stop transmission) bit is checked using an interrupt or
polling. At this time, the MNR (master NACK reception) is checked. When the NACK is
returned, an error routine is executed to re-transmit the last byte data.
2
C Bus Interface
2
C module latches the FSB value and enters the stop state.