HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 321

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
Pins IRL0 to IRL3 can be used for four independent interrupt requests by setting the IRLM bit in
ICR to 1.
When independent interrupt requests are used, the interrupt priority levels can be set in interrupt
priority level setting register D (IPRD).
9.4.4
Peripheral Module Interrupts
Peripheral module interrupts are interrupts generated by peripheral modules.
Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the
interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT value as a
branch offset in the exception handling routine.
A priority level from 15 to 0 can be set for each module by means of IPRA to IPRD and
INTPRI00 to INTPRI0C.
The interrupt mask level bits (IMASK3 to IMASK0) in SR are not affected by peripheral module
interrupt processing.
Updating of the interrupt source flag and interrupt enable flag of a peripheral module should only
be carried out when the BL bit in SR is set to 1. To prevent erroneous interrupt acceptance from an
interrupt source that should have been updated, first read the on-chip peripheral register containing
the relevant flag, then clear the BL bit to 0. This will secure the necessary timing internally. When
updating a number of flags, there is no problem if only the register containing the last flag updated
is read from.
If flag updating is performed while the BL bit is cleared to 0, the program may jump to the
interrupt handling routine when the INTEVT value is 0. In this case, interrupt processing is
initiated due to the timing relationship between the flag update and interrupt request recognition
within this LSI. Processing can be continued without any problem by executing an RTE
instruction.
Rev. 2.00 Feb. 12, 2010 Page 237 of 1330
REJ09B0554-0200