HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1039
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Bit
4
3
2
1
0
Bit
Name
CWRE
DTBUSY
DTBUSY_
TU
—
REQ
Initial
Value
0
0
—
0
0
R/W
R
R
R
R
R
Description
Command Register Write Enable
Indicates whether the CMDR command is being
transmitted or has been transmitted.
0: The CMDR command has been transmitted, or the
1: The CMDR command is waiting for transmission or
Data Busy
Indicates command execution status. Indicates that the
card is in the busy state after the command sequence
of a command without data transfer which includes the
busy state in the response, or a command with write
data has been ended.
0: Idle state waiting for a command, or command
1: Card is in the data busy state after command
Data Busy Pin Status
Indicates the MCDAT pin level. By reading this bit, the
MCDAT level can be monitored.
0: A low level is input to the MCDAT pin.
1: A high level is input to the MCDAT pin.
Reserved
This bit is always read as 0. The write value should
always be 0.
Interrupt Request
Indicates whether an interrupt is requested or not. An
interrupt request is the logical OR of the INTSTR0 and
INTSTR1 flags. The INTSTR0 and INTSTR1 flags set is
controlled by the enable bits in INTCR0 and INTCR1.
0: No interrupt requested.
1: Interrupt requested.
START bit in CMDSTRT has not been set yet, so
the new command can be written.
is being transmitted. If a new command is written,
a malfunction will result.
sequence execution in progress
sequence termination.
Rev. 2.00 Feb. 12, 2010 Page 955 of 1330
REJ09B0554-0200
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