HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 444

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
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The MPX interface timing is shown below.
When the MPX interface is used for areas 1 to 6, a bus size of 32 bits should be specified by
BCR2.
In wait control, waits can be specified by WCR2 and waits can be inserted by the RDY pin.
In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to
0.
Rev. 2.00 Feb. 12, 2010 Page 360 of 1330
REJ09B0554-0200
Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level)= 0 for the DMAC.
Figure 10.43 Example of 32-Bit Data Width MPX Connection
CKIO
RD/FRAME
D31 − D0
CSn
RD/WR
RDY
BS
DACKn
(DA)
SH7760
D31–D0
RD/WR
CKIO
RDY
CSn
RD
BS
Tm1
A
Tmd1w
Tmd1
D0
MPX device
CLK
CS
BS
FRAME
WE
I/O31–I/O0
RDY

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