HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 782

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 I
Note: * If FSB is not set with this timing, the stop condition (P) may not be issued correctly.
19.5.2
1.
2.
3.
4.
5.
6.
7.
19.6
19.6.1
In order to set up the master interface to transmit a data packet on the I
steps.
(1) Load the clock control register:
(a) Set SCL clock generation divider (SCGD) to 01h.
(b) Set clock division ratio to 2h.
Rev. 2.00 Feb. 12, 2010 Page 698 of 1330
REJ09B0554-0200
concerning the timing with which FSB is set in application system, in particular, check the
interrupt response and handling times carefully.
(SCL frequency of 400 kHz)
(Peripheral clock: 33 MHz and I
Clear the ESG bit to 0 when the RDF bit is set to 1 by receiving data for the byte count
specified by the register.
The receive byte count specified by the RTRG bits in ICFCR can be selected from 1 to 16.
When the receive byte count reaches the specified count, an RDF interrupt is generated (RXIE
= 1) and receive operation is stopped. The ACK signal is automatically returned until the RDF
bit is set to 1.
Read all the receive data in the receive FIFO by the CPU when the RDF interrupt occurs.
(Dummy-reading or reading before an RDF interrupt generation is not allowed.) However, if
issuing a STOP condition is needed, carry out step 6.
To resume receive operations, read all the receive data in the receive FIFO with FSB = 0 and
then clear the RDF flag in ICFSR to 0. (Modify the RTRG bits before clearing the RDF flag,
if necessary.)
In order to issue a STOP condition, set the FSB bit to 1 and wait at least on bit period. Then
read all the receive data in the receive FIFO and clear the RDF flag to 0. (The FSB bit must be
set only in this timing).
In order to forcibly stop the receive operation before the receive byte count reaches the RTRG
setting, manually control (start/stop) the FSCL bit and the FSDA bit in ICMCR and read data
for the receive byte count indicated by ICRFDR from the receive FIFO.
Master Receiver Operation (FIFO Buffer Mode)
Programming Examples
Master Transmitter (Single Buffer Mode)
2
C Bus Interface
2
C internal clock (IICck): 11 MHz)
2
C bus, take the following