HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 473

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3.2
DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer.
During a DMA transfer, they indicate the next destination address. In single address mode, the
DAR value is ignored when a device with DACK has been specified as the transfer destination.
A 16-bit, 32-bit, 64-bit, or 32-byte boundary address should be specified when performing a 16-
bit, 32-bit, 64-bit, or 32-byte data transfer, respectively. If a different address is specified, an
address error will be detected and the DMAC will halt.
Initial value:
Initial value:
Notes: 1. Make the setting of bit 0, bits 1 and 0, bits 2 to 0, or bits 4 to 0 to match the boundary
R/W:
R/W:
Bit:
Bit:
2. An external address is 29 bits long. Bits 31 to 29 in both SAR and DAR are not used in
2. An external address is 29 bits long. Bits 31 to 29 in both SAR and DAR are not used in
DMA Destination Address Register (DAR)
R/W
R/W
is specified for a data transfer via the external bus or if an address for an on-chip
peripheral module that does not exist is specified.
DMA transfers. Therefore, clearing bits 31 to 29 to 0 in both SAR and DAR is
recommended.
when specifying a 16-bit, 32-bit, 64-bit, or 32-byte boundary address, respectively. If
an address is specified regardless of the boundary, an address error will be detected and
the DMAC stops operation on all channels (AE (address error flag) bit in DMAOR is
1). The DMAC will also detect an address error and stop operation if an area 7 address
is specified for a data transfer via the external bus or if an address for an on-chip
peripheral module that does not exist is specified.
DMA transfers. Therefore, clearing bits 31 to 29 to 0 in both SAR and DAR is
recommended.
31
15
-
-
R/W
R/W
30
14
-
-
R/W
R/W
29
13
-
-
R/W
R/W
28
12
-
-
R/W
R/W
27
11
-
-
R/W
R/W
26
10
-
-
R/W
R/W
25
9
-
-
R/W
R/W
24
8
-
-
R/W
R/W
23
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 389 of 1330
R/W
R/W
22
6
-
-
R/W
R/W
21
5
-
-
R/W
R/W
20
4
-
-
R/W
R/W
19
3
-
-
REJ09B0554-0200
R/W
R/W
18
-
2
-
R/W
R/W
17
1
-
-
R/W
R/W
16
-
0
-