HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 696

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Rev. 2.00 Feb. 12, 2010 Page 612 of 1330
REJ09B0554-0200
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
B. The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
the first is checked.
No
No
No
No
Figure 17.12 Sample Serial Reception Flowchart (2)
Read receive data in SCFRDR
and ORER flag in SCLSR, to 0
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
in SCFSR,
BRK = 1?
DR = 1?
ER = 1?
End
Yes
Yes
Yes
Yes
[1] Whether a framing error or parity error
[2] When a break signal is received,
has occurred in the receive data that
is to be read from SCFRDR can be
ascertained from the FER and PER
bits in SCFSR.
receive data (H'00) is not transferred
to SCFRDR.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.
When a break handling is completed
and a receive signal returns to 1, the
receive data transfer resumes.