HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 704

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In serial reception, the SCIF operates as described below.
1. The SCIF is initialized internally in synchronization with the input or output of the
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
Figure 17.20 shows an example of the operation for reception in synchronous mode.
Rev. 2.00 Feb. 12, 2010 Page 620 of 1330
REJ09B0554-0200
synchronization clock.
After receiving the data, the SCIF checks whether the receive data can be transferred from
SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an
overrun error is detected in the error check, reception cannot continue.
interrupt (RXI) request is generated.
If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI)
request is generated.
Synchronization
Figure 17.20 Sample SCIF Reception Operation in Synchronous Mode
Serial data
ORER
clock
RDF
Figure 17.19 Sample Serial Reception Flowchart (2)
interrupt
request
RXI
Bit 7
RXI interrupt handler
No
SCFRDR and RDF
flag cleared to 0 by
Bit 0
LSB
Data read from
One frame
Clear ORER flag in SCLSR to 0
Overrun error handling
Error handling
ORER = 1?
MSB
Bit 7
RXI interrupt
End
request
Yes
Bit 0
Bit 1
BRI interrupt request
Bit 6
by overrun error
Bit 7