HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1132

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Typical operations when channel 1 (AN1) is selected in single mode are described below. Figure
29.2 shows a timing diagram for this example.
1. Select single mode as the operating mode (MDS1 = 0 and MDS0 = 0), AN1 as the input
2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At
3. Since ADF = 1, ADIE = 1, and DMASL = 0, an ADI interrupt is generated.
4. The A/D interrupt processing routine starts.
5. The A/D interrupt processing routine reads and processes the A/D conversion result
6. After reading ADF = 1, write 0 in the ADF bit.
7. Execution of the A/D interrupt processing routine ends. After this, when the ADST bit is set to
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channel (CH1 = 0 and CH0 = 1), and enable A/D interrupt requests (ADIE = 1). Then start
A/D conversion (ADST = 1).
the same time, the ADF bit is set to 1, the ADST bit is cleared to 0, and the A/D converter
becomes idle.
(ADDRB).
1, A/D conversion starts and steps 2 to 7 are repeated.
Figure 29.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Channel 1 (AN1)
Channel 2 (AN2)
Channel 3 (AN3)
Channel 0 (AN0)
ADDRC
ADDRD
ADDRA
ADDRB
ADST
ADF
ADI
A/D
conversion
starts
Note: * Vertical arrows (
Idle
A/D conversion (1)
Set*
Interrupt
occurs
↓
) indicate instruction execution by software.
Idle
Idle
Idle
Clear*
Idle
A/D conversion result (1)
Read result
A/D conversion (2)
Set*
A/D conversion result (2)
Read result
Clear*
Idle