HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 18

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
19.3.5 Master Control
Register (ICMCR)
19.3.6 Master Status
Register (ICMSR)
19.3.14 Receive FIFO
Data Count Register
(ICRFDR)
19.3.15 Transmit FIFO
Data Count Register
(ICTFDR)
Rev. 2.00 Feb. 12, 2010 Page xvi of lxxxii
REJ09B0554-0200
Page
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Revision (See Manual for Details)
Table amended
Table amended
Description amended
H'0000 0000 indicates that ICRXD contains no receive data,
while H'0000 0010 indicates that it holds 16 bytes of receive
data.
Description amended
H'0000 0000 indicates that ICTXD contains no transmit data,
while H'0000 0010 indicates that it holds 16 bytes of transmit
data.
Bit
1
Bit
2
0
Bit Name
FSB
Bit Name
MDT
MAT
Initial Value
0
Initial Value
0
0
R/W
R/W
R/W
R/W*
R/W*
Description
Force Stop onto the Bus
Setting FSB to 1 will have the master issue a stop
onto the bus at the end of the current transfer. If
ESG is also 1, the master immediately issues a
start and begins transmitting a new data packet. If
ESG is 0, the master enters the idle state.
Set FSB to 1 when the TEND flag is set to 1
during transmission in the FIFO buffer mode, or
when the RDF flag is set to 1 during reception in
the FIFO buffer mode.
In single buffer mode, when the last bit of a byte
is transmitted/received, the I
FSB value and enters the STOP state. Therefore,
to stop the transfer after a specified number of
bytes are transferred, the FSB bit must be set to 1
before the last byte is transferred.
Note: Check section 19.7, Usage Notes, when
Description
Master Data Transmission
The master has transmitted a byte of data to the
slave on the bus. This status bit becomes 1 after
the falling edge of SCL during the last data bit
transmission.
Master Address Transmission
The master has transmitted the slave address
byte of a data packet. This bit becomes 1 after the
falling edge of SCL during the output of the ack bit
which is sent after an address.
using this bit.
2
C module latches the