HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 410

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Bus State Controller (BSC)
(6) Single Write
The basic timing chart for single write access is shown in figure 10.19. In a single write operation,
a WRITA command that performs auto-precharge is issued in cycle Tc1 following the Tr cycle
where the ACTV command is output. In the write cycle, the write data is output at the same time
as the write command. For the write with auto-precharge command, precharging of the relevant
bank is performed in the synchronous DRAM after completion of the write command, and
therefore no command can be issued for the synchronous DRAM until precharging is completed.
Consequently, in addition to the precharge wait cycle Tpc used in a read access, cycle Trwl is also
added as a wait cycle until precharging is started following the write command for delaying
issuance of a new command for the synchronous DRAM during this period. Bits TRWL2 to
TRWL0 in MCR can be used to specify the number of Trwl cycles. DACK is asserted two cycles
before the data write cycle.
This LSI supports 4- or 8-burst-length read and write operations of synchronous DRAM. Dummy
cycles are therefore generated even with single write operations.
Rev. 2.00 Feb. 12, 2010 Page 326 of 1330
REJ09B0554-0200