HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 670

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: X: Don't care
17.3.7
SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the
SCIF.
SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to
flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they
must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be
modified.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 586 of 1330
REJ09B0554-0200
Bit
1
0
R/W:
Bit:
1. Outputs a clock with a frequency 16 times the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
Bit Name
CKE1
CKE0
Serial Status Register (SCFSR)
15
R
0
-
14
-
R
0
13
R
0
-
Initial Value
0
0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
10
R
0
-
R
9
-
0
Description
Clock Enable 1, 0
These bits select the SCIF clock source and
whether to enable or disable the clock output from
the SCIF_CLK pin. The CKE1 and CKE0 bits are
used together to specify whether the SCIF_CLK
pin functions as a serial clock output pin or a serial
clock input pin. Note however that the CKE0 bit
setting is valid only when an internal clock is
selected as the SCIF clock source (CKE1 = 0).
When an external clock is selected (CKE1 = 1),
the CKE0 bit setting is invalid. The CKE1 and
CKE0 bits must be set before determining the
SCIF's operating mode with SCSMR.
Asynchronous mode
00: Internal clock/SCIF_CLK pin functions as port
01: Internal clock/SCIF_CLK pin functions as
1X: External clock/SCIF_CLK pin functions as
Synchronous mode
0X: Internal clock/SCIF_CLK pin functions as
1X: External clock/SCIF_CLK pin functions as
R
8
0
-
synchronization clock output
synchronization clock input
clock output*
clock input*
R/W*
ER
7
0
1
TEND
R/W*
6
1
2
1
1
TDFE
R/W*
5
1
1
BRK
R/W*
4
0
1
FER
3
0
R
PER
2
0
R
RDF
R/W*
1
0
1
R/W*
DR
0
0
1