HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 510

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

RS3
0
11.4.2
DMA transfer requests are basically generated at either the data transfer source or destination, but
they can also be issued by external devices or on-chip peripheral modules that are neither the
source nor the destination.
Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral
module request. The transfer request mode is selected by bits RS3 to RS0 in CHCR0 to CHCR7
and settings of DMARSRA and DMARSRB.
(1) Auto-Request Mode
The DMAC can automatically generate a transfer request signal internally in Auto-Request Mode
when receiving no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer. Setting the DE bit in CHCR of the channel to be used and the DME bit in DMAOR to 1
starts the transfer. However, the TE bit in CHCR of the channel to be used and the NMIF and AE
bits in DMAOR must all be 0.
(2) External Request Mode
In this mode, the DMAC performs a transfer in response to a transfer request signal (DREQ) from
an external device. Select one of the modes shown in table 11.6 according to the application
system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts
when DREQ is input. The DS bits in CHCR0 to CHCR7 and bits DS3 to DS0 in DMARCR are
used to select either falling edge detection or low level detection of the DREQ signal (level
detection with DS = 0, edge detection with DS = 1).
The source of the transfer request does not have to be the data transfer source or destination.
Table 11.6 Selecting External Request Mode with RS Bits
Rev. 2.00 Feb. 12, 2010 Page 426 of 1330
REJ09B0554-0200
RS2
0
DMA Transfer Requests
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Single address
mode
Transfer Source
External memory,
memory-mapped external
device, or on-chip
peripheral module
External memory or
memory-mapped external
device
External device with
DACK
Transfer Destination
External memory,
memory-mapped external
device, or on-chip
peripheral module
External device with
DACK
External memory or
memory-mapped external
device